1. Field
Exemplary embodiments of the present invention relate to a one-time program cell array circuit including a plurality of one-time program cells.
2. Description of the Related Art
A one-time program memory cell is a memory cell whose data logic value cannot be changed once the memory cell is programmed. The one-time program memory cell includes memory cells using laser fuses and e-fuses.
FIG. 1 is a schematic of an e-fuse that is formed of a transistor, and the e-fuse that operates as either a resistor or a capacitor.
Referring to FIG. 1, the e-fuse includes a transistor T, and a power source voltage is supplied to a gate G while a ground voltage is supplied to a drain/source D/S.
If a power source voltage of an ordinary level that the transistor T may tolerate is supplied to the gate G, then the e-fuse may operate as a capacitor C. Therefore, no current flows between the gate G and the drain D or the source S. However, if a high voltage that the transistor T cannot tolerate is supplied to the gate G, then the gate oxide of the transistor T is destroyed to short the gate G and the drain source D/S. As a result, the e-fuse may operate as a resistor R. Therefore, current flows between the gate G and the drain/source D/S.
Based on these results, the data of an e-fuse is recognized from the resistance value between the gate G and the drain/source D/S. The data of the e-fuse may be recognized by (1) enlarging the size of the transistor T, or (2) using an amplifier, instead of increasing the size of the transistor T, and sensing the current flowing through the transistor T. If the transistor T is enlarged, the data of the e-fuse may be recognized without performing a sensing operation. The above two methods, however, have concerns regarding dimensional restrictions because the transistor T that constitutes the e-fuse has to be enlarged or each e-fuse has to be equipped with an amplifier for amplifying data.
U.S. Pat. No. 7,269,047 discloses a technology for forming an e-fuse in a type of an e-fuse array in order to reduce the area occupied by the e-fuse.
FIG. 2 is a block view illustrating a conventional e-fuse cell array 200.
Referring to FIG. 2, the e-fuse cell array 200 includes memory cells 201 to 216 that are arrayed in N rows and M columns. The memory cells 201 to 216 include memories M1 to M16 and switches S1 to S16, respectively. Each of the memories M1 to M16 is an e-fuse that has the characteristics of a resistor or a capacitor based on whether it is ruptured or not. In other words, the e-fuses M1 to M16 may be regarded as resistive memories that store data based on the level of resistance. The switches S1 to S16 electrically connect the memories M1 to M16 with column lines BL1 to BLM under the control of row lines WLR1 to WLRN.
Hereafter, it is assumed that a second row is a selected row, and a Mth column is a selected column, in other words, it is assumed that a memory cell 208 is a selected memory cell. The voltages supplied to the selected memory cell 208 and unselected memory cells 201 to 207 and 209 to 216 during a program and read operation are described below.
Program Operation
The selected row line WLR2 is enabled and the other row lines WLR1 and WLR3 to WLRN are disabled. As a result, switches S5 to S8 are turned on, while switches S1 to S4 and S9 to S16 are turned off. A high voltage that could destroy the gate oxide of the e-fuse, which is generally generated by pumping a power source voltage, is supplied to the program/read line WLP2 of the selected row, and a voltage of a lower level, e.g., a ground voltage, is supplied to the other program/read lines WLP1, and WLP3 to WLPN. The selected column line BLM is coupled with a data access circuit, and the unselected column lines BL1 to BLM-1 float. If an input data is a program data, e.g., ‘1’, then the data access circuit drives the selected column line BLM at a low-level voltage to program (or rupture) the memory M8 of the selected memory cell 208. If the input data is not a program data, e.g., ‘0’, then the data access circuit drives the selected column line BLM at a high-level voltage so that the memory M8 of the selected memory cell 208 may not be programmed.
Because the unselected column lines BL1 to BLM-1 float, the memories M5 to M7 may not be programmed even though a high voltage is supplied to the gates.
Read Operation
The selected row line WLR2 is enabled, and the other row lines WLR1 and WLR3 to WLRN are disabled. As a result, switches S5 to S8 are turned on, and switches S1 to S4 and S9 to S16 are turned off. A voltage of an appropriate level for a read operation is supplied to the program/read line WLP2 of the selected row, and a low voltage, e.g., a ground voltage, is supplied to the other program/read lines WLP1, and WLP3 to WLPN. The selected column line BLM is coupled with a data access circuit, and the unselected column lines BL1 to BLM-1 float. If current flows through the selected column line BLM, then the data access circuit may recognize that the memory M8 is programmed. In other words, the data access circuit may recognize that the data of the selected memory cell 208 is ‘1’. If no current flows through the selected column line BLM, then the data access circuit may recognize that the memory M8 is not programmed. In other words, the data access circuit may recognize that the data of the selected memory cell 208 is ‘0’.
Although it is illustrated herein that one column line BLN is selected among the column lines BL1 to BLM, a plurality of column lines may be selected at one time. In other words, a plurality of memory cells that belong to one row may be simultaneously programmed or read.
FIG. 3 is a block view of a conventional one-time program cell array circuit including the e-fuse cell array 200 shown in FIG. 2.
Referring to FIG. 3, the one-time program cell array circuit includes the e-fuse cell array 200 shown in FIG. 2, a row circuit 310, a column decoding circuit 320, and a data access circuit 330.
The row circuit 310 controls the row lines WLR1 to WLRN and the program/read lines to perform a program operation or a read operation, as mentioned above. A row address ROW_ADD inputted to the row circuit 310 designates a row selected among the multiple rows, and a program/read signal PG/RD directs a program operation or a read operation.
The column decoding circuit 320 electrically connects the data access circuit 330 with a selected column line that is selected based on a column address COL_ADD among the multiple column lines BL1 to BLM. In this exemplary embodiment of the present invention, a case where eight column lines are selected among the multiple column lines BL1 to BLM.
The data access circuit 330 controls the access of data of the selected column lines that are selected by the column decoding circuit 320. During a program operation, the data access circuit 330 controls the selected column lines selected based on an input data DATA<0:7> to be programmed or not to be programmed. During a read operation, the data access circuit 330 senses whether current flows through the selected column lines or not, and it outputs an output data DATA<0:7>.
The one-time program cell array circuit including an e-fuse may store data if the gate oxide of the transistor is destroyed, or may not store data if the gate oxide of the transistor is not destroyed. The gate oxide may be or may not be easily destroyed based on the characteristics of the transistor. In short, a resistive memory device may have a failure based on the characteristics of the transistor. Therefore, it is required to develop a technology that may increase the reliability of a one-time program cell array circuit.